Conventionally, a silicon-on-insulator (SOI) device has a basic structure with a semiconductor region, in which circuit elements such as transistors are formed, that is surrounded by an insulating layer, including on a bottom surface. In such an arrangement, junction capacitance, and the like, is reduced, thereby enabling high speed operation.
In the formation of semiconductor devices, in order to realize a desired circuit operation, such as a logic function, it is necessary to connect various circuit elements with wiring layers. In addition, it is necessary to form power source wirings to provide an operation voltage. Such an operating voltage can generally include a power source potential (typically a positive or negative potential) along with a ground potential.
Typically, a large amount of current flows through power source wirings. In addition, it is necessary to provide such wirings to a large number of circuit elements throughout a semiconductor device. As a result, the area occupied by conventional power source wirings can be of considerable size. This can limit the way in which other wirings, such as signal wirings, can be laid out in the semiconductor device.
A conventional technique for simplifying a power source wiring utilizing a conductive stud is disclosed in, by example, Japanese Patent Publication 10-209468 and set forth in FIG. 10.
In FIG. 10, a semiconductor layer 3 is surrounded by an insulating layer 2 formed on a semiconductor substrate 1. A source region 4 and drain region 5 of a metal-oxide-semiconductor (MOS) transistor are formed, with semiconductor layer 3 providing a transistor channel region. In addition, a gate electrode 7 is formed on the channel region over a gate insulating film 6. A drain region 5 is connected with a wiring 10 by way of a conductor 8 within a contact hole formed in an interlayer insulating film 9. Further, a conductive stud 11 is provided that penetrates interlayer insulating film 9, source region 4, semiconductor layer 3, and insulating layer 2, to reach semiconductor substrate 1. The source region 4, semiconductor layer 3 and substrate 1 are electrically connected to one another by way of conductive stud 11. Thus, a semiconductor substrate 1 can be used as a source for supplying a power source potential or a ground potential.
The above conventional approach can have limitations, however. According to such a conventional technique, the only types of transistors that can be employed are those in which a source region 4 and semiconductor layer 3 are maintained at the same potential. Such an arrangement cannot realize circuits like those utilized in a transfer gate, for example, in which source/drain regions have varying potentials with respect to a corresponding substrate (e.g., or body or channel). Thus, such a need cannot be addressed with the conventional conductive stud structure shown in FIG. 10.
In addition, complementary MOS (CMOS) is currently the mainstream technology. In CMOS circuits, two types of power source wirings are typically necessary: a first power source wiring for providing a positive (or negative) potential and a second power source wiring for providing a ground potential. The structure shown in FIG. 10 addresses the supply of only one power source wiring by way of a conductive stud, and not two, as is needed in CMOS technology.
In light of the above, it would be desirable to arrive at some way of providing a power supply wiring for a semiconductor device, such as an SOI device, that does not suffer from the conventional limitations noted above.